In advanced complementary metal oxide semiconductor (CMOS) technologies gate oxides are very thin and operating on supply voltages (Vdd) are confined in small ranges, such as 1V for example. MOS transistor structures in the integrated circuit (IC) core are thus very fragile and high voltages can be generated by electrostatic charging in the manufacturing chain, at the chip assembly or in applications, which might destroy the IC.
Between the IC core and the outside world, input/output (IO) cells may be organized in a ring, which are responsible for Vdd level shifting, for noise immunity, and—at the same time—for protection of the IC core from ESD shocks or other temporary excessive voltages that can occur at the pins. In order to fulfill this protection function, each I/O cell may comprise a big transistor, generally of the N-channel MOS (NMOS) type, which represents an alternative, low resistive path when it is activated, thereby short-circuiting the supply line Vdd to ground potential (Gnd) or another lower reference potential. Thereby, it can be ensured that ESD charge or other excessive charge does not pass through or influence the active circuitry.
However, creating a very conductive current path in case of an ESD event or other excessive temporary voltages to allow high current flow (e.g. about 4 A) requires very high current capability design for the I/O protection network. To this end, the use of MOS clamps has the advantage that, with good models, the ESD behavior can be easily simulated and the design of the I/O ring can be optimized for the smallest size. Metal rail resistances and high current path design have a crucial importance in technologies with gate lengths below 100 nm (e.g. CMOS090, CMOS065, CMOS045 and below). In order to improve the speed of reaction of trigger circuits which produce a pulse to be applied to the gate of e.g. NMOS ESD clamps in each I/O in case of the detection of a very fast rising edge on a special rail (which may be called “ESD_boost”), a distributed and boosted ESD network has been developed.
FIG. 3 shows a schematic circuit diagram of a exemplary distributed boosted ESD network as disclosed for example in Michael Stockinger, James W. Miller et al, “Boosted and Distributed Rail Clamp Networks for ESD protection in Advanced CMOS Technologies”, Proc. Of EOS/ESD Symposium 2003. In FIG. 3, two adjacent I/O cells 10-1 and 10-2 are shown. The PMOS and NMOS transistors are used as output buffer transistors. The LNPN and LPNP bipolar transistors are lateral bipolar transistors inherent to the MOS structures. In case the I/O cells 10-1 and 10-2 were not protected or the protection is failing to trigger, then the output buffer transistors would be destroyed because of the high current passing through the associated LNPN or LPNP. The drains of the output buffer transistors are directly tied to respective I/O pads 14-1 and 14-2.
The ESD protection network consists of two low resistive metal lines or rails vdde and gnde, carrying all ESD transient current, one boost line or rail esd_boost connected through a diode A2 to the respective I/O pads 14-1 and 14-2 (i.e., a rail which does not carry a lot of current and serves to supply a remote trigger circuit 20), diodes A1 and B which carry all ESD current and closing the loop, and respective ESD clamps 12-1 and 12-1, which are large NMOS devices driven by the remote trigger circuit 20. The trigger circuit 20 can be implemented in several ways, for example a so-called slew-rate detector with monostable trigger pulse generator. When a very fast rising pulse (for example 4V in less than 10 ns) occurs on the boost rail esd_boost, a pulse is immediately fired by the trigger circuit 20 for a predetermined time period (e.g. about 1 μs) within which it is considered that the ESD event is finished and all electrostatic charge has been evacuated. If the rise time of the boost rail esd_boost is longer (for example in a normal power-up event), then there is no pulse generated by the trigger circuit 20. The energy for triggering the ESD clamps 12-1 and 12-2 via a special trigger line or rail esd_trigger is taken from the ESD energy. Thus, the trigger circuit 20 operates even if power supply of the integrated circuit is active or switched on.
Furthermore, in FIG. 3, the clamps 12-1 and 12-2 are distributed and each one takes more or less current depending on their gate-source drive voltages VGS which vary because of the voltage drop along the ground rail gnde. Therefore, several trigger circuits 20 have to be provided, on one side because of the voltage drop along the ground rail gnde, and on the other side because the clamps 12-1 and 12-2 themselves are large transistors and there is a need to provide a certain driving strength of the trigger circuits 20.
However, a disadvantageous side effect of the large clamps 12-1 and 12-2 is that current leakage during normal operation increases with the width of the clamp. Typical leakage values are in the order of a few picoamperes per micron width at room temperature and are increasing with the temperature. If the clamp is very wide and/or operation temperature is high, the leakage current can be in the order of tens of microamperes, and in ICs with a large number of connection pins (for example 1000 pins) total leakage can be in the order of milliamperes just for these clamps in normal operation. Moreover, a large clamp occupies large area in each I/O cell in prejudice of the active circuitry and requires a large trigger circuit buffer to drive the gates of several clamps fast and efficiently enough.